Unifying Logical and Physical Layout Representations via Heterogeneous Graphs for Circuit Congestion Prediction

ArXi:2603.11075v1 Announce Type: cross As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations.