AI RESEARCH
Effective Capacitance Modeling Using Graph Neural Networks
arXiv CS.LG
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ArXi:2507.03787v2 Announce Type: replace Static timing analysis is a crucial stage in the VLSI design flow that verifies the timing correctness of circuits. Timing analysis depends on the placement and routing of the design, but at the same time, placement and routing efficiency depend on the final timing performance. VLSI design flows can benefit from timing-related prediction to better perform the earlier stages of the design flow. Effective capacitance is an essential input for gate delay calculation, and finding exact values requires routing or routing estimates.