Formally Verifying Analog Neural Networks Under Process Variations Using Polynomial Zonotopes

ArXi:2605.10474v1 Announce Type: cross Analog neural networks are gaining attention due to their efficiency in terms of power consumption and processing speed. However, since analog neural networks are implemented as physical circuits, they are highly sensitive to manufacturing process variations, which can cause large deviations from the nominal model. We present a polynomial-based model that resembles the performance of the neuron circuit under process variations.