AI RESEARCH
Heuristic-Based Merging of HPC Traces to Extend Hardware Counter Coverage
arXiv CS.LG
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ArXi:2605.15832v1 Announce Type: cross This work extends a framework for predicting the performance of High-Performance Computing (HPC) workloads using Machine Learning (ML). A common limitation in performance modeling is the restricted number of hardware counters that can be collected simultaneously. To address this, we propose a heuristic-based methodology to merge execution traces from multiple runs, each instrumented with a different set of hardware counters. Our approach matches computation bursts across executions by analyzing MPI structure, timing, and communication patterns.