AI RESEARCH
Continuous-Flow Data-Rate-Aware CNN Inference on FPGA
arXiv CS.LG
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ArXi:2601.19940v2 Announce Type: replace Among hardware accelerators for deep-learning inference, data flow implementations offer low latency and high throughput capabilities. In these architectures, each neuron is mapped to a dedicated hardware unit, making them well-suited for field-programmable gate array (FPGA) implementation. Previous unrolled implementations mostly focus on fully connected networks because of their simplicity, although it is well known that convolutional neural networks (CNNs) require fewer computations for the same accuracy.